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1

[IEEE 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers - San Francisco, CA, USA (2007.02.11-2007.02.15)] 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers - A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery

Harwood, Mike, Warke, Nirmal, Simpson, Richard, Leslie, Tom, Amerasekera, Ajith, Batty, Sean, Colman, Derek, Carr, Eugenia, Gopinathan, Venu, Hubbins, Steve, Hunt, Peter, Joy, Andy, Khandelwal, Pulkit

Year:

2007

Language:

english

File:

PDF, 952 KB

english, 2007

2

The impact of technology scaling on ESD robustness and protection circuit design

Amerasekera, A., Duvvury, C.

Journal:

IEEE Transactions on Components Packaging and Manufacturing Technology Part A

Year:

1995

Language:

english

File:

PDF, 744 KB

english, 1995

3

ESD failure modes: characteristics mechanisms, and process influences

Amerasekera, A., van den Abeelen, W., van Roozendaal, L., Hannemann, M., Schofield, P.

Journal:

IEEE Transactions on Electron Devices

Year:

1992

Language:

english

File:

PDF, 1.06 MB

english, 1992

4

Advanced CMOS protection device trigger mechanisms during CDM

Duvvury, C., Amerasekera, A.

Journal:

IEEE Transactions on Components Packaging and Manufacturing Technology Part C

Year:

1996

Language:

english

File:

PDF, 198 KB

english, 1996

5

High-current failure model for VLSI interconnects under short-pulse stress conditions

K. Banerjee, A. Amerasekera, N. Cheung, Chenming Hu

Journal:

IEEE Electron Device Letters

Year:

1997

Language:

english

File:

PDF, 109 KB

english, 1997

6

[ESD Assoc Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 - Reno, NV, USA (6-8 Oct. 1998)] Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347) - ESD-related process effects in mixed-voltage sub-0.5 μm technologies

Gupta, V., Amerasekera, A., Ramaswamy, S., Tsao, A.

Year:

1998

Language:

english

File:

PDF, 670 KB

english, 1998

7

ESD issues for advanced CMOS technologies

Charvaka Duvvury, Ajith Amerasekera

Journal:

Microelectronics Reliability

Year:

1996

Language:

english

File:

PDF, 679 KB

english, 1996

8

An investigation of BiCMOS ESD protection circuit elements and applications in submicron technologies

Ajith Amerasekera, Amitava Chatterjee

Journal:

Journal of Electrostatics

Year:

1993

Language:

english

File:

PDF, 796 KB

english, 1993

9

Photon emission as a tool for esd failure localization and as a technique for studying ESD phenomena

Marcel Hannemann, Ajith Amerasekera

Journal:

Quality and Reliability Engineering International

Year:

1991

Language:

english

File:

PDF, 640 KB

english, 1991

10

Self-heating effects in basic semiconductor structures

Amerasekera, A., Chang, M.-C., Seitchik, J.A., Chatterjee, A., Mayaram, K., Chern, J.-H.

Journal:

IEEE Transactions on Electron Devices

Year:

1993

Language:

english

File:

PDF, 1.01 MB

english, 1993

11

Design methodology and optimization of gate-driven NMOS ESD protection circuits in submicron CMOS processes

Chen, J.Z., Amerasekera, E.A., Duvvury, C.

Journal:

IEEE Transactions on Electron Devices

Year:

1998

Language:

english

File:

PDF, 510 KB

english, 1998

12

Characterization and modeling of second breakdown in NMOST's for the extraction of ESD-related process and design parameters

Amerasekera, A., van Roozendaal, L., Bruines, J., Kuper, F.

Journal:

IEEE Transactions on Electron Devices

Year:

1991

Language:

english

File:

PDF, 819 KB

english, 1991

13

Imaging of the complications of peripherally inserted central venous catheters

S.S.H. Amerasekera, C.M. Jones, R. Patel, M.J. Cleasby

Journal:

Clinical Radiology

Year:

2009

Language:

english

File:

PDF, 937 KB

english, 2009

14

[IEEE 1997 IEEE International Reliability Physics Symposium Proceedings. 35th Annual - Denver, CO, USA (8-10 April 1997)] 1997 IEEE International Reliability Physics Symposium Proceedings. 35th Annual - Characterization of contact and via failure under short duration high pulsed current stress

Banerjee, K., Amerasekera, A., Dixit, G., Cheung, N., Chenming Hu,

Year:

1997

Language:

english

File:

PDF, 1.33 MB

english, 1997

15

ESD: a pervasive reliability concern for IC technologies

Duvvury, C., Amerasekera, A.

Journal:

Proceedings of the IEEE

Year:

1993

Language:

english

File:

PDF, 1.67 MB

english, 1993

16

[IEEE Proceedings of 1994 IEEE International Reliability Physics Symposium - San Jose, CA, USA (1994.04.11-1994.04.14)] Proceedings of 1994 IEEE International Reliability Physics Symposium RELPHY-94 - Designing latchup robustness in a 0.35 /spl mu/m technology

Amerasekera, A., Selvam, S.T., Chapman, R.A.

Year:

1994

Language:

english

File:

PDF, 469 KB

english, 1994

17

[IEEE 1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual - San Diego, CA, USA (23-25 March 1999)] 1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296) - Analysis of snapback behavior on the ESD capability of sub-0.20 μm NMOS

Amerasekera, A., Gupta, V., Vasanth, K., Ramaswamy, S.

Year:

1999

Language:

english

File:

PDF, 588 KB

english, 1999

18

[IEEE Proceedings of International Reliability Physics Symposium - Dallas, TX, USA (1996.04.30-1996.05.2)] Proceedings of International Reliability Physics Symposium RELPHY-96 - Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations

Amerasekera, A., Ramaswamy, S., Mi-Chang Chang,, Duvvury, C.

Year:

1996

Language:

english

File:

PDF, 834 KB

english, 1996

19

[IEEE Proceedings of 17th Annual Electrical Overstress/Electrostatic Discharge Symposium - Phoenix, AZ, USA (1995.09.12-1995.09.14)] Electrical Overstress/Electrostatic Discharge Symposium Proceedings - Advanced CMOS protection device trigger mechanisms during CDM

Duvvury, C., Amerasekera, A.

Year:

1995

Language:

english

File:

PDF, 1.28 MB

english, 1995

20

[IEEE Proceedings of International Reliability Physics Symposium - Dallas, TX, USA (1996.04.30-1996.05.2)] Proceedings of International Reliability Physics Symposium RELPHY-96 - Characterization of VLSI circuit interconnect heating and failure under ESD conditions

Banerjee, K., Amerasekera, A., Chenming Hu,

Year:

1996

Language:

english

File:

PDF, 887 KB

english, 1996

21

[ESD Assoc Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 - Anaheim, CA, USA (26-28 Sept. 2000)] Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476) - Substrate pump NMOS for ESD protection applications

Duvvury, C., Ramaswamy, S., Amerasekera, A., Cline, R.A., Andresen, B.H., Gupta, V.

Year:

2000

Language:

english

File:

PDF, 1.08 MB

english, 2000

22

[IEEE International Electron Devices Meeting - Washington, DC, USA (10-13 Dec. 1995)] Proceedings of International Electron Devices Meeting - Substrate triggering and salicide effects on ESD performance and protection circuit design in deep submicron CMOS processes

Amerasekera, A., Duvvury, C., Reddy, V., Rodder, M.

Year:

1995

Language:

english

File:

PDF, 350 KB

english, 1995

23

[IEEE International Electron Devices Meeting 1991 [Technical Digest] - Washington, DC, USA (8-11 Dec. 1991)] International Electron Devices Meeting 1991 [Technical Digest] - Design and simulation of a 4 kV ESD protection circuit for a 0.8 mu m BiCMOS process

Chatterjee, A., Polgreen, T., Amerasekera, A.

Year:

1991

Language:

english

File:

PDF, 341 KB

english, 1991

24

[IEEE 2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual - San Jose, CA, USA (10-13 April 2000)] 2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059) - Process and layout dependent substrate resistance modeling for deep sub-micron ESD protection devices

Zhang, X.Y., Banerjee, K., Amerasekera, A., Gupta, V., Zhiping Yu,, Dutton, R.W.

Year:

2000

Language:

english

File:

PDF, 760 KB

english, 2000

25

[ESD Assoc 18th Annual Electrical Overstress/Electrostatic Discharge Symposium - Orlando, FL, USA (10-12 Sept. 1996)] Proceedings Electrical Overstress/Electrostatic Discharge Symposium - EOS/ESD analysis of high-density logic chips

Ramaswamy, S., Duvvury, C., Amerasekera, A., Reddy, V., Kang, S.M.

Year:

1996

Language:

english

File:

PDF, 450 KB

english, 1996

26

[IEEE International Electron Devices Meeting. IEDM Technical Digest - Washington, DC, USA (7-10 Dec. 1997)] International Electron Devices Meeting. IEDM Technical Digest - A unified substrate current model for weak and strong impact ionization in sub-0.25 μm NMOS devices

Ramaswamy, S., Amerasekera, A., Chang, M.-C.

Year:

1997

Language:

english

File:

PDF, 337 KB

english, 1997

27

Technology design for high current and ESD robustness in a deep submicron CMOS process

A. Amerasekera, R. Chapman

Year:

1994

Language:

english

File:

PDF, 262 KB

english, 1994

28

[IEEE 1994 IEEE International Electron Devices Meeting - San Francisco, CA, USA (11-14 Dec. 1994)] Proceedings of 1994 IEEE International Electron Devices Meeting - Electrothermal behavior of deep submicron nMOS transistors under high current snapback (ESD/EOS) conditions

Amerasekera, A., Seitchik, J.A.

Year:

1994

Language:

english

File:

PDF, 348 KB

english, 1994

29

[IEEE International Electron Devices Meeting. Technical Digest - San Francisco, CA, USA (8-11 Dec. 1996)] International Electron Devices Meeting. Technical Digest - Correlating drain junction scaling, salicide thickness, and lateral NPN behavior, with the ESD/EOS performance of a 0.25 μm CMOS process

Amerasekera, A., McNeil, V., Rodder, M.

Year:

1996

Language:

english

File:

PDF, 377 KB

english, 1996

30

An investigation of the nature and mechanisms of ESD damage in NMOS transistors

E.A. Amerasekera, D.S. Campbell

Journal:

Solid-State Electronics

Year:

1989

Language:

english

File:

PDF, 612 KB

english, 1989

31

Electrostatic pulse breakdown in nmos devices

E. A. Amerasekera, D. S. Campbell

Journal:

Quality and Reliability Engineering International

Year:

1986

Language:

english

File:

PDF, 835 KB

english, 1986

32

ESD in integrated circuits

Ajith Amerasekera, Jan Verwey

Journal:

Quality and Reliability Engineering International

Year:

1992

Language:

english

File:

PDF, 1.43 MB

english, 1992

33

Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high-current simulations

Amerasekera, A., Mi-Chang Chang, Duvvury, C., Ramaswamy, S.

Journal:

IEEE Circuits and Devices Magazine

Year:

1997

Language:

english

File:

PDF, 389 KB

english, 1997

34

Introduction to the Special Issue on the 2009 Symposium on VLSI Circuits

Mizuno, M., Amerasekera, A.

Journal:

IEEE Journal of Solid-State Circuits

Year:

2010

Language:

english

File:

PDF, 441 KB

english, 2010

35

Introduction to the Special Issue on the 2010 Symposium on VLSI Circuits

Amerasekera, A., Nagata, M.

Journal:

IEEE Journal of Solid-State Circuits

Year:

2011

Language:

english

File:

PDF, 334 KB

english, 2011

36

The Changing Design Landscape

Amerasekera, Ajith

Journal:

IEEE Design & Test of Computers

Year:

2008

Language:

english

File:

PDF, 110 KB

english, 2008

37

[IEEE International Electron Devices Meeting. IEDM Technical Digest - Washington, DC, USA (7-10 Dec. 1997)] International Electron Devices Meeting. IEDM Technical Digest - A shallow trench isolation for sub-0.13 μm CMOS technologies

Nandakumar, M., Sridhar, S., Nag, S., Mei, P., Rogers, D., Hanratty, M., Amerasekera, A., Chen, I.-C.

Year:

1997

Language:

english

File:

PDF, 459 KB

english, 1997

38

[IEEE 2012 IEEE International Electron Devices Meeting (IEDM) - San Francisco, CA, USA (2012.12.10-2012.12.13)] 2012 International Electron Devices Meeting - Ultra low power design and future device interactions

Amerasekera, Ajith, Bittlestone, Clive

Year:

2012

Language:

english

File:

PDF, 2.68 MB

english, 2012

39

[IEEE 2013 IEEE International Solid-State Circuits Conference (ISSCC 2013) - San Francisco, CA (2013.2.17-2013.2.21)] 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers - A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems

Qazi, M., Amerasekera, A., Chandrakasan, A. P.

Year:

2013

Language:

english

File:

PDF, 416 KB

english, 2013

40

A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13-$\mu \hbox{m}$ CMOS for Nonvolatile Processing in Digital Systems

Qazi, Masood, Amerasekera, Ajith, Chandrakasan, Anantha P.

Journal:

IEEE Journal of Solid-State Circuits

Year:

2014

Language:

english

File:

PDF, 2.35 MB

english, 2014

41

[IEEE 2014 IEEE International Solid- State Circuits Conference (ISSCC) - San Francisco, CA, USA (2014.02.9-2014.02.13)] 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) - ES2: Data centers to support tomorrow's cloud

Chang, Leland, Amerasekera, Ajith, Hashimoto, Takashi, Chang, Leland

Year:

2014

Language:

english

File:

PDF, 2.77 MB

english, 2014

42

[Widerkehr & Associates 1996 Symposium on VLSI Technology. Digest of Technical Papers - Honolulu, HI, USA (11-13 June 1996)] 1996 Symposium on VLSI Technology. Digest of Technical Papers - A shallow trench isolation study for 0.25/0.18 μm CMOS technologies and beyond

Chatterjee, A., Esquivel, J., Nag, S., Ali, I., Rogers, D., Taylor, K., Joyner, K., Mason, M., Mercer, D., Amerasekera, A., Houston, T., Chen, I.-C.

Year:

1996

Language:

english

File:

PDF, 295 KB

english, 1996

43

[IEEE Comput. Soc 16th International Conference on VLSI Design. Concurrently with the 2nd International Conference on Embedded Systems Design - New Delhi, India (4-8 Jan. 2003)] 16th International Conference on VLSI Design, 2003. Proceedings. - Optimization of 1.8V I/O circuits for performance, reliability at the 100 nm technology node

Menezes, V., Keshav, C.B., Gupta, S., Roopashree, M., Krishnan, S., Amerasekera, A., Palau, G.

Year:

2003

Language:

english

File:

PDF, 392 KB

english, 2003

44

[IEEE Proceedings of 1995 IEEE International Reliability Physics Symposium - Las Vegas, NV (1995.04.4-1995.04.6)] 33rd IEEE International Reliability Physics Symposium - Trends for deep submicron VLSI and their implications for reliability

Chatterjee, P.K., Hunter, W.R., Amerasekera, A., Aur, S., Duvvury, C., Nicollian, P.E., Ting, L.M., Ping Yang,

Year:

1995

Language:

english

File:

PDF, 1011 KB

english, 1995

45

[IEEE 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07) - Bangalore, India (2007.01.6-2007.01.10)] 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07) - Concurrent Optimization of Technology and Design for Nano CMOS

Amerasekera, Ajith

Year:

2007

Language:

english

File:

PDF, 165 KB

english, 2007

46

[IEEE 2000 Symposium on VLSI Circuits. Digest of Technical Papers - Honolulu, HI, USA (15-17 June 2000)] 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103) - Addressing ESD for microprocessors and ASICs in 21st century technologies

Amerasekera, A.

Year:

2000

Language:

english

File:

PDF, 439 KB

english, 2000

47

[IEEE Technical Papers. International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan (June 3-5, 1997)] Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications - A Shallow-'ikench Isolation Study For 0.18pm Cmos Technology With Emphasis On The Effects Of Well Design, Channel-stop Implants, Trenchl Depth, And Salicide Process

Murtaza, S.S., Chatterjee, A., Mei, P., Amerasekera, A., Nicollian, P., Kittl, J., Breedijk, T., Hanratty, M., Nag, S., Ali, I., Rogers, D., Chen, I.-C.

Year:

1997

Language:

english

File:

PDF, 366 KB

english, 1997

48

[IEEE Proceedings Electrical Overstress/Electrostatic Discharge Symposium - Orlando, FL, USA (1997.09.25-1997.09.25)] Proceedings Electrical Overstress/Electrostatic Discharge Symposium - Design Methodology For Optimizing Gate Driven Esd Protection Circuits In Submicron Cmos Processes

Julian Zhiliang Chen,, Amerasekera, A., Duvvury, C.

Year:

1997

Language:

english

File:

PDF, 1.08 MB

english, 1997

49

[IEEE Comput. Soc 2002 3rd International Symposium on Quality Electronic Design - San Jose, CA, USA (18-21 March 2002)] Proceedings International Symposium on Quality Electronic Design - A robust digital delay line architecture in a 0.13 μm CMOS technology node for reduced design and process sensitivities

Raha, P., Randall, S., Jennings, R., Helmick, B., Amerasekera, A., Haroun, B.

Year:

2002

Language:

english

File:

PDF, 249 KB

english, 2002

50

[IEEE 1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual - San Diego, CA, USA (23-25 March 1999)] 1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296) - Investigation of self-heating phenomenon in small geometry vias using scanning Joule expansion microscopy

Banerjee, K., Wu, G., Igeta, M., Amerasekera, A., Majumdar, A., Hu, C.

Year:

1999

Language:

english

File:

PDF, 491 KB

english, 1999